Comparators are frequently used in analog-to-digital converters (ADCs) to make decisions on input signal voltage or current levels, where the decision is usually made with respect to a reference signal. On a circuit level, the comparator may be implemented using clocked latch circuitry. The clocked latch circuitry causes the output of the comparator to latch on high or low supply levels. When the input signal is very close to the predefined reference threshold, any noise or distortion in the signal path may lead to a wrong decision at the comparator output. Therefore, a pre-amplifier may be introduced before the clocked latch circuitry to amplify the signal to a desirable level.
Signal amplification enhances the overall conversion accuracy of the comparator having a pre-amplifier and a clocked latch. In a typical Successive Approximation Register (SAR) based ADC design, a capacitive digital-to-analog converter (CDAC) holds the input sampled signal at the comparator inputs. In high-speed ADCs, smaller capacitors values of the CDAC are essential to realize high conversion rates. However, a CDAC having smaller capacitors is more susceptible to picking up parasitic noise coupling, which makes kick-back noise an obstacle for ultra-high-speed ADCs. While the pre-amplifier serves as an isolating stage between the clocked latch and the capacitive DAC, it still contributes significant level of transient disturbance.
Therefore, a circuit for implementing an analog-to-digital converter that reduces the kick-back noise would be beneficial.